This invention relates generally to charge-coupled device (CCD) integrated circuits, and, more particularly, to CCD circuits that include an array of full adder cells useful, for example, in implementing multi-bit digital multipliers or dividers.
CCDs have established themselves as a technology with low power consumption and high packing density for both analog and digital applications. However, CCDs have not gained widespread acceptance as a viable digital technology, in part because they are not generally considered to be well adapted for the efficient implementation of complex circuits such as multi-bit multipliers and dividers.
Attempts have been made in the past to produce pipelined carry-save multipliers utilizing CCD technology alone. The multipliers have included an array of full adder cells, one suitable version of which is described in U.S. Pat. No. 4,464,728, issued to James G. Nash and entitled "Charge Coupled Device Ripple Adder with Nearly Instantaneous Carry Propagation." Although such a CCD digital multiplier achieves high throughput per unit power and is relatively small in size, it is not believed to be as small in size as is possible. Significantly, more than one-half of the multiplier's total area is occupied by CCD delay circuitry that coordinates the arrival of bits at each of the multiplier's successive logic stages.
Accordingly, there is a need for a complex CCD integrated circuit such as a pipelined digital multiplier or divider that is even more efficient than those previously available. In particular, there is a need for such a CCD circuit that can perform the same function as has been performed by CCD circuits in the pass, but with a reduced total size and complexity. The present invention fulfills this need.